ALLGEMEINE BESCHREIBUNG

The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable  N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.

 

FEATURES

400 MHz bandwidth

2.7 V to 3.3 V power supply

Separate charge pump supply (VP) allows extended

tuning voltage in 3 V systems

Programmable charge pump currents

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

104 MHz phase detector

 

ANWENDUNGEN

Clock conditioning

Clock generation

IF LO generation

 

ANWENDUNGSINFORMATIONEN

VERY LOW JITTER ENCODE CLOCK FOR HIGH SPEED CONVERTERS

The converter used in this application is an AD9215-80, a 12-bit converter that accepts up to an 80 MHz encode clock. To realize a stable low jitter clock, use a 77.76 MHz, narrow-band VCXO. This example assumes a 19.44 MHz reference clock. To minimize the phase noise contribution of the ADF4002, the smallest multiplication factor of 4 is used. Thus, the R divider is programmed to 1, and the N divider is programmed to 4.  The charge pump output of the ADF4002 (Pin 2) drives the loop filter. The loop filter bandwidth is optimized for the best possible rms jitter, a key factor in the signal-to-noise ratio (SNR) of the ADC. Too narrow a bandwidth allows the VCXO noise to dominate at small offsets from the carrier frequency. Too wide a bandwidth allows the ADF4002 noise to dominate at offsets where the VCXO noise is lower than the ADF4002 noise. Thus, the intersection of the VCXO noise and the ADF4002 inband noise is chosen as the optimum loop filter bandwidth.  The design of the loop filter uses the ADIsimPLL (Version 3.0) and is available as a free download from www.analog.com/ADIsimPLL. The rms jitter is measured at <1.2 ps. This level is lower than the maximum allowable 6 ps rms required to ensure the theoretical SNR performance of 59 dB for this converter.  The SPI interface is used to control the ADF4002, and the USB interface helps control the operation of the AD9215-80. The controller board sends back FFT information to the PC that, if using an ADC analyzer, provides all conversion results from the ADC.

PFD

As the ADF4002 permits both R and N counters to be programmed to 1, the part can effectively be used as a standalone PFD and charge pump. This is particularly useful in either a clock cleaning application or a high performance LO. Additionally, the very low normalized phase noise floor (−222 dBc/Hz) enables very low in-band phase noise levels. It is possible to operate the PFD up to a maximum frequency of 104 MHz. The charge pump output integrates into a stable control voltage for the VCXO, and the output from the VCXO is divided down to the desired PFD frequency using an external divider.

INTERFACING

The ADF4002 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When the latch enable (Pin LE) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. For more information.The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz, or one update every 1.2 μs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds.