Allgemeine Beschreibung

The MAX6369–MAX6374 are pin-selectable watchdog timers that supervise microprocessor (μP) activity and signal when a system is operating improperly. During normal operation, the microprocessor should repeatedly toggle the watchdog input (WDI) before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse can be used to reset the μP or interrupt the system to warn of processing errors.

The MAX6369–MAX6374 are flexible watchdog timer supervisors that can increase system reliability through notification of code execution errors. The family offers several pin-selectable watchdog timing options to match a wide range of system timing applications:

Watchdog startup delay: provides an initial delay before the watchdog timer is started.

Watchdog timeout period: normal operating watchdog timeout period after the initial startup delay.

Watchdog output/timing options: open drain (100ms) or push-pull (1ms).

The MAX6369–MAX6374 operate over a +2.5V to +5.5V supply range and are available in miniature 8-pin SOT23 packages.

 

Vorteile und Merkmale

Precision Watchdog Timer for Critical μP Applications

Pin-Selectable Watchdog Timeout Periods

Pin-Selectable Watchdog Startup Delay Periods

Ability to Change Watchdog Timing Characteristics Without Power Cycling

Open-Drain or Push-Pull Pulsed Active-Low Watchdog Output

Watchdog Timer Disable Feature

+2.5V to +5.5V Operating Voltage

8μA Low Supply Current

No External Components Required

Miniature 8-Pin SOT23 Package

AEC-Q100 Qualified (MAX6369KA/V+ and MAX6374KA/V+ Only)

 

Anwendungen

Embedded Control Systems

Industrial Controllers

Critical μP and Microcontroller (μC) Monitoring

Automobilindustrie

Telekommunikation

Networking

 

Detaillierte Beschreibung

The MAX6369–MAX6374 are flexible watchdog circuits for monitoring μP activity. During normal operation, the internal timer is cleared each time the μP toggles the WDI with a valid logic transition (low to high or high to low) within the selected timeout period (tWD). The WDO remains high as long as the input is strobed within the selected timeout period. If the input is not strobed before the timeout period expires, the watchdog output is asserted low for the watchdog output pulse width (tWDO). The device type and the state of the three logic control pins (SET0, SET1, and SET2) determine watchdog timing characteristics. The three basic timing variations for the watchdog startup delay and the normal watchdog timeout period are summarized below :

Watchdog Startup Delay:

Provides an initial delay before the watchdog timer is started. Allows time for the μP system to power up and initialize before assuming responsibility for normal watchdog timer updates. Includes several fixed or pin-selectable startup delay options from 200μs to 60s, and an option to wait for the first watchdog input transition before starting the watchdog timer.

Watchdog Timeout Period:

Normal operating watchdog timeout period after the initial startup delay.

A watchdog output pulse is asserted if a valid watch dog input transition is not received before the timeout period elapses.

Eight pin-selectable timeout period options for each device, from 30μs to 60s.

Pin-selectable watchdog timer disable feature.

Watchdog Output/Timing Options:

Open drain,active low with 100ms minimum watchdog output pulse (MAX6369/MAX6371/MAX6373).

Push-pull, active low with 1ms minimum watchdog output pulse (MAX6370/MAX6372/MAX6374).

Each device has a watchdog startup delay that is initiated when the supervisor is first powered or after the user modifies any of the logic control set inputs. The watchdog timer does not begin to count down until the completion of the startup delay period, and no watchdog output pulses are asserted during the startup delay. When the startup delay expires, the watchdog begins counting its normal watchdog timeout period and waiting for WDI transitions. The startup delay allows time for the μP system to power up and fully initialize before assuming responsibility for the normal watchdog timer updates. Startup delay periods vary between the different devices and may be altered by the logic control set pins. To ensure that the system generates no undesired watchdog outputs, the routine watchdog input transitions should begin before the selected minimum startup delay period has expired.