DESCRIPCIÓN GENERAL

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The ADC output data are routed directly to the external 12-bit LVDS output port.  Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a  3-wire, SPI-compatible serial interface. The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

 

PRODUCTOS DESTACADOS

  1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
  2. Fast overrange and threshold detect.
  3. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz.
  4. 3-pin, 1.8 V SPI port for register programming and readback.
  5. Pin compatibility with the AD9642, allowing a simple migration up to 14 bits, and with the AD6672.

 

CARACTERÍSTICAS

SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS

SFDR = 87 dBc at 185 MHz AIN and 250 MSPS

−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS

Total power consumption: 360 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs

Integer 1-to-8 input clock divider (625 MHz maximum input)

Sample rates of up to 250 MSPS

Internal ADC voltage reference

Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer

Serial port control

Modos de ahorro de energía

 

APLICACIONES

Comunicaciones

Sistemas de radio de diversidad

Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE

I/Q demodulation systems

Sistemas de antenas inteligentes

General-purpose software radios

Equipo de ultrasonidos

Broadband data applications

 

TEORÍA DE FUNCIONAMIENTO

The AD9634 can sample any fS/2 frequency segment from dc to 250 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance.  Programming and control of the AD9634 are accomplished using a 3-pin, SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9634 architecture consists of a front-end sample-andhold circuit, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a  final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.

For more parameters, please refer to the Datasheets.