Descripción

The NB7L1008M is a high performance differential 1:8 Clock/Data fanout buffer. The NB7L1008M produces eight identical output copies of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50  termination resistors that are accessed through the VT pin. This feature allows the NB7L1008M to accept various logic standards, such as LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:8 fanout design was optimized for low output skew applications. The NB7L1008M is a member of the GigaComm family of high performance clock products.

 

Características

Input Data Rate > 12 Gb/s Typical

Data Dependent Jitter < 20 ps

Maximum Input Clock Frequency > 8 GHz Typical

Random Clock Jitter < 0.8 ps RMS

Low Skew 1:8 CML Outputs, < 25 ps max

Multi−Level Inputs, accepts LVPECL, CML, LVDS

160 ps Typical Propagation Delay

45 ps Typical Rise and Fall Times

Differential CML Outputs, 400 mV Peak−to−Peak, Typical

Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V

Internal Input Termination Resistors, 50

VREFAC Reference Output

QFN−32 Package, 5 mm x 5 mm

−40°C to +85°C Ambient Operating Temperature

These are Pb−Free Devices

 

Más información

PIN DESCRIPTION

In the differential configuration when the input termination pin (VT) is connected to a commontermination voltage or left open, and if no signal is applied on IN/IN , then the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50Ωsource termination resistors.

All VCC and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.

MAXIMUM RATINGS

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.

CML outputs loaded with 50  to VCC for proper operation.

Input and output parameters vary 1:1 with VCC.

Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.

Vth is applied to the complementary input when operating in single−ended mode.

VIHD, VILD, VID, and VCMR parameters must be complied with simultaneously

AC CHARACTERISTICS

Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.

Measured using a 400 mV source, 50% duty cycle 1 GHz clock source. All outputs must be loaded with external 50Ω to VCC. Input edge rates 40 ps (20% − 80%).

Output voltage swing is a single−ended measurement operating in differential mode.

VIHDMIN≥1100 mV.

Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.

Within device skew compares coincident edges.

Device to device skew is measured between outputs under identical transition

Additive CLOCK jitter with 50% duty cycle clock signal.

Additive Peak−to−Peak jitter with input NRZ data at PRBS23.

Input voltage swing is a single−ended measurement operating in differential mode.

JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.