Descripción

This dual Schmitt-Trigger buffer is designed for 1.65V to 5.5-V VCC operation.
The SN74LVC2G17 device contains two buffers and performs the Boolean function Y = A. The device functions as two independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

 

Características

• Schmitt-Trigger inputs provide hysteresis
• Available in the Texas Instruments NanoFree™ Package
• Supports 5-V VCC Operación
• Inputs Accept Voltages to 5.5 V
• Maxtpd of 5.4 ns at 3.3 V
• LowPower Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 Vat VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-Down Mode Operation and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESDProtection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model

 

Aplicaciones

• AVReceivers
• Audio Docks: Portable
• Blu-ray Players and Home Theater
• MP3Players/Recorders
• Personal Digital Assistants (PDAs)
• Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital
• Solid State Drives (SSDs): Client and Enterprise
• TVs: LCD/Digital and High-Definition (HDTVs)
• Tablets: Enterprise
• Video Analytics: Server
• Wireless Headsets, Keyboards, and Mice

 

Absolute Maximum Ratings

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)The value of VCC is provided in the Recommended Operating Conditions table.

 

Clasificaciones ESD

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

 

Visión general

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

 

Descripción

• 1.65 V to 5.5 V operating voltage range
• Allows down voltage translation
– 5Vto3.3 V
– 5Vor3.3 Vto 1.8 V
• Inputs accept voltages to 5.5 V
– 5-Vtolerance on input pin
• Ioff feature
– Allows voltage on the inputs and outputs when VCC is 0 V
– Able to reduce leakage when VCC is 0 V
• Schmitt-Trigger Input can improve the noise immunity capability

 

Detailed Parameter Introduction

Información sobre la solicitud

The SN74LVC2G17 device contains two buffers and performs the Boolean function Y = A. The device functions as two independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions should be considered to prevent ringing.

Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states.