Descripción

The STM32G030x6/x8 mainstream microcontrollers are based on high performance Arm Cortex-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.
Los dispositivos incorporan una unidad de protección de memoria (MPU), memorias integradas de alta velocidad (8 Kbytes de SRAM y hasta 64 Kbytes de memoria de programa Flash con protección contra lectura y escritura), DMA, una amplia gama de funciones de sistema, E/S mejoradas y periféricos. Los dispositivos ofrecen interfaces de comunicación estándar (dos I²C, dos SPI / un I²S y dos USART), un ADC de 12 bits (2,5 MSps) con hasta 19 canales, un RTC de bajo consumo, un temporizador PWM de control avanzado, cuatro temporizadores de propósito general de 16 bits, dos temporizadores watchdog y un temporizador SysTick.
The devices operate within ambient temperatures from -40 to 85°C and with supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes allows the design of low-power applications. VBAT direct battery input allows keeping RTC and backup registers powered.
Los dispositivos se presentan en paquetes de 8 a 48 pines.

 

Características

• Core: Arm 32-bit Cortex-M0+ CPU, frequency up to 64 MHz
•-40°C to 85°C operating temperature
- Recuerdos
– Up to 64 Kbytes of Flash memory with protection
- 8 Kbytes de SRAM con comprobación de paridad HW
• CRC calculation unit
• Reset and power management
- Rango de tensión: de 2,0 V a 3,6 V
- Reinicio de encendido/apagado (POR/PDR)
– Low-power modes: Sleep, Stop, Standby
- Alimentación VBAT para RTC y registros de reserva
- Gestión del reloj
- Oscilador de cristal de 4 a 48 MHz
- Oscilador de cristal de 32 kHz con calibración
- RC interno de 16 MHz con opción PLL
- Oscilador RC interno de 32 kHz (±5 %)
• Up to 44 fast I/Os
- Todas asignables a vectores de interrupción externos
- Múltiples E/S tolerantes a 5 V
• 5-channel DMA controller with flexible mapping
• 12-bit, 0.4 µs ADC (up to 16 ext. channels)
- Hasta 16 bits con sobremuestreo por hardware
- Rango de conversión: 0 a 3,6V
• 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby
- Interfaces de comunicación
– Two I²C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
– Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
– Two SPIs (32 Mbit/s) with 4-to 16-bit programmable bitframe, one multiplexed with I²S interface
• Development support: serial wire debug (SWD)
• All packages ECOPACK 2 compliant

 

Unidad de protección de memoria

La unidad de protección de memoria (MPU) se utiliza para gestionar los accesos de la CPU a la memoria y evitar que una tarea corrompa accidentalmente la memoria o los recursos utilizados por cualquier otra tarea activa.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

 

Memoria Flash integrada

Los dispositivos STM32G030x6/x8 disponen de hasta 64 Kbytes de memoria Flash integrada para almacenar código y datos.
Se pueden configurar protecciones flexibles gracias a los bytes opcionales:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
- Nivel 0: sin protección de lectura
– Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is Selected
– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible.