Descripción

STM32H750xB devices are based on the high-performance Arm Cortex-M7 32-bit RISC core operating at up to 480 MHz. The Cortex -M7 core features a floating point unit (FPU) which supports Arm double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H750xB devices incorporate high-speed embedded memories with a flash memory of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2×32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.

All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

  • Standard peripherals

– Four I2Cs

– Four USARTs, four UARTs and one LPUART

– Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization.

– Four SAI serial audio interfaces

– One SPDIFRX interface

– One SWPMI (Single Wire Protocol Master Interface)

– Management Data Input/Output (MDIO) slaves

– Two SDMMC interfaces

– A USB OTG full-speed and a USB OTG high-speed interface with full-speed capability (with the ULPI)

– One FDCAN plus one TT-FDCAN interface

– An Ethernet interface

– Chrom-ART Accelerator

– HDMI-CEC

  • Advanced peripherals including

– A flexible memory control (FMC) interface

– A Quad-SPI flash memory interface

– A camera interface for CMOS sensors

– An LCD-TFT display controller

– A JPEG hardware compressor/decompressor

 

Arm Cortex-M7 with FPU

The Arm Cortex-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency.

The Cortex-M7 processor is a highly efficient high-performance featuring:

  • Six-stage dual-issue pipeline
  • Dynamic branch prediction
  • Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
  • 64-bit AXI interface
  • 64-bit ITCM interface
  • 2×32-bit DTCM interfaces

The following memory interfaces are supported:

  • Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
  • Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses
  • AXI Bus interface to optimize Burst transfers
  • Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

 

Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is generated.