Características

  • Operating voltage range 2 V to 5.5 V
  • Low supply current 1 μA
  • Integrated test mode
  • Single Smart Reset™ push-button input with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal input pull-up resistor
  • Push-button controlled reset pulse duration
  • Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed
  • Option 2: defined output reset pulse duration (tREC), factory-programmed
  • Single reset output
  • Active-low or active-high
  • Push-pull or open drain with optional pull-up resistor
  • Fixed Smart Reset input logic voltage levels
  • Operating temperature: -40 °C to 85 °C
  • UDFN6 package 1.00 mm x 1.45 mm
  • ECOPACK®2 (RoHS compliant, Halogen-Free)

 

Aplicaciones

  • Mobile phones, smartphones, PDAs
  • e-books
  • MP3 players
  • Games
  • Portable navigation devices
  • Any application that requires delayed reset push-button response for improved system stability

Descripción

The Smart ResetTM devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input pushbutton is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time tSRC causes a hard reset of the processor through the reset output.

The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time (tSRC). The reset output (RST) is asserted after the Smart Reset input is held active for the selected tSRC delay time. The RST output remains asserted either until the SR input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC (i.e. factory-programmed). The device fully operates over a broad VCC range from 2.0 V to 5.5 V.

 

Test mode

After pulling SR up to VTEST (VCC + 1.4 V) or above, the counter starts to count the initial shortened tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for tREC (if tREC option is used) or stays low as long as overvoltage on SR is detected (if tREC option is not used). This is feedback, and the user only knows that the device is locked in test mode. Each time the SR input is connected to ground in test mode, a shortened tSRC-SHORT (tSRC/128) is used instead of regular tSRC (0.5 s – 10 s). In this way the device can be quickly tested without repeating test mode triggering. Return to normal mode is possible by performing a new startup of the device (i.e. VCC goes to 0 V and back to its original state).

The advantages of this solution are its high glitch immunity, user feedback regarding entry into test mode, and testability within the full VCC range.

 

Power supply (VCC)

This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the STM6519 device as possible.

 

Power-up sequence

In normal mode, if different input side (SR) and VCC voltage domains are used, power-on sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode entry: there should not be logic high present on the SR input before the VCC power-up.

However VCC and V(SR) rising at the same time is OK (e.g. if both are in the same voltage domain), the device will then safely start into normal operating mode, with RST output inactive (in High-Z mode for open-drain option).