DESCRIPTION GÉNÉRALE

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The ADC output data are routed directly to the external 12-bit LVDS output port.  Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a  3-wire, SPI-compatible serial interface. The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

 

POINTS FORTS DU PRODUIT

Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.

Fast overrange and threshold detect.

Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz.

3-pin, 1.8 V SPI port for register programming and readback.

Pin compatibility with the AD9642, allowing a simple migration up to 14 bits, and with the AD6672.

 

CARACTÉRISTIQUES

SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS

SFDR = 87 dBc at 185 MHz AIN and 250 MSPS

−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS

Total power consumption: 360 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs

Integer 1-to-8 input clock divider (625 MHz maximum input)

Sample rates of up to 250 MSPS

Internal ADC voltage reference

Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer

Serial port control

Energy-saving power-down modes

 

CANDIDATURES

Communications

Diversity radio systems

Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Matériel d'échographie

Broadband data applications

 

THÉORIE DU FONCTIONNEMENT

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9634 is a differential switched-capacitor circuit that has been designed to attain optimum performance when processing a differential input signal.  The clock signal alternatively switches the input between sample mode and hold mode . When the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within ½ clock cycle.  A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, reduce the shunt capacitors. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs; and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters” for more information on this subject.  For best dynamic performance, match the source impedances driving VIN+ and VIN− and differentially balance the inputs.

Input Common Mode

The analog inputs of the AD9634 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance. An on-board commonmode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 µF capacitor, as described in the Applications Information section. Place this decoupling capacitor close to the pin to minimize the series resistance and inductance between the part and this capacitor.