DESCRIPTION

The LT8640S-2/LT8643S-2 synchronous step-down regulator features Silent Switcher architecture designed to minimize EMI emissions while delivering high efficiency at high switching frequencies. Peak current mode control with a 30ns minimum on-time allows high step-down ratios even at high switching frequencies.The LT8643S-2 has external compensation to enable current sharing and fast transient response at high switching frequencies.

Burst Mode operation enables ultralow standby current consumption, forced continuous mode can control frequency harmonics across the entire output load range, or spread spectrum operation can further reduce EMI emissions.

 

FEATURES

Silent Switcher Architecture

Ultralow EMI Emissions

Optional Spread Spectrum Modulation

High Efficiency at High Frequency

Up to 96% Efficiency at 1MHz, 12VIN to 5VOUT

Up to 95% Efficiency at 2MHz, 12VIN to 5VOUT

Wide Input Voltage Range: 3.4V to 42V

6A Maximum Continuous, 7A Peak Output

Ultralow Quiescent Current Burst Mode® Operation

2.5μA IQ Regulating 12VIN to 3.3VOUT (LT8640S-2)

Output Ripple < 10mVP-P

External Compensation: Fast Transient Response and Current Sharing (LT8643S-2)

Fast Minimum Switch On-Time: 30ns

Low Dropout Under All Conditions: 100mV at 1A

Forced Continuous Mode

Adjustable and Synchronizable: 200kHz to 3MHz

Output Soft-Start and Tracking

Small 24-Lead 4mm × 4mm LQFN Package

AEC-Q100 Qualified for Automotive

 

Applications

Automotive and Industrial Supplies

General Purpose Step-Down

 

OPERATION

To improve efficiency across all loads, supply current to internal circuitry can be sourced from the BIAS pin when biased at 3.3V or above. Else, the internal circuitry will draw current from VIN. The BIAS pin should be connected to VOUT if the LT8640S-2/LT8643S-2 output is programmed at 3.3V to 25V.

The VC pin optimizes the loop compensation of the switching regulator based on the programmed switching frequency, allowing for a fast transient response. The VC pin also enables current sharing and a CLKOUT pin enables synchronizing other regulators to the LT8643S-2.

Comparators monitoring the FB pin voltage will pull the PG pin low if the output voltage varies more than ±8% (typical) from the set point, or if a fault condition is present.

The oscillator reduces the LT8640S-2/LT8643S-2’s operating frequency when the voltage at the FB pin is low. This frequency foldback helps to control the inductor current when the output voltage is lower than the programmed value which occurs during start-up or overcurrent conditions. When a clock is applied to the SYNC/MODE pin, the SYNC/MODE pin is floated, or held DC high, the frequency foldback is disabled and the switching frequency will slow down only during overcurrent conditions.

 

APPLICATIONS INFORMATION

Low EMI PCB Layout

The LT8640S-2/LT8643S-2 is specifically designed to minimize EMI emissions and also to maximize efficiency when switching at high frequencies. For optimal performance the LT8640S-2/LT8643S-2 requires the use of multiple VIN bypass capacitors.

Two small 1μF capacitors should be placed as close as possible to the LT8640S-2/LT8643S-2, one capacitor on each side of the device (CIN1, CIN2). A third capacitor with a larger value, 2.2μF or higher, should be placed near CIN1 or CIN2.

For more detail and PCB design files refer to the Demo Board guide for the LT8640S-2/LT8643S-2.

Note that large, switched currents flow in the LT8640S-2/ LT8643S-2 VIN and GND pins and the input capacitors. The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the VIN and GND pins. Capacitors with small case size such as 0603 are optimal due to lowest parasitic inductance.

The input capacitors, along with the inductor and output capacitors, should be placed on the same side of the circuit board, and their connections should be made on that layer. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. The SW and BOOST nodes should be as small as possible. Finally, keep the FB and RT nodes small so that the ground traces will shield them from the SW and BOOST nodes.