DESCRIPTION GÉNÉRALE

The AD3541R is a low drift, single channel, ultra-fast, 12-/16-bit accuracy, voltage output digital-to-analog converter (DAC) that can be configured in multiple voltage span ranges. The AD3541R operates with a fixed 2.5 V reference.

Each DAC incorporates three drift compensating feedback resistors for the internal transimpedance amplifier (TIA) that scales the output voltage. The device has five preconfigured output voltage ranges: 0 V to 2.5 V, 0 V to 5 V, 0 V to 10 V, −5 V to +5 V, and −2.5 V to +7.5 V.

The AD3541RBCPZ16 (hereafter referred to as AD3541R-16) can operate in fast mode for maximum speed or precision mode for maximum accuracy. The AD3541RBCPZ12 (hereafter referred to as AD3541R-12) has a single operation mode.

The serial peripheral interface (SPI) can be configured in dual SPI and single SPI (classic SPI) mode with single date rate (SDR) or double data rate (DDR), with logical levels from 1.2 V to 1.8 V.

The AD3541R is specified over the extended industrial temperature range (–40°C to +105°C).

 

CARACTÉRISTIQUES

12-/16-bit resolution

16 MUPS single channel rate in fast mode

11 MUPS single channel rate in precision mode

78 ns small signal settling time to 0.1% accuracy

100 ns large signal settling time to 0.1% accuracy

Ultrasmall glitch: <50 pV×s

Ultralow latency: 5 ns

THD: −105 dB at 1 kHz for AD3541R-16 and −95 dB at 1 kHz for AD3541R-12

5 selectable output voltage ranges

1.2 V and 1.8 V logic level compatible

Single (classic) and dual SPI modes

Multiple error detectors, both analog and digital domains

2.5 V internal voltage reference, 10 ppm/°C maximum TC

Small package: 4 mm × 4 mm LFCSP

 

CANDIDATURES

L'instrumentation

Hardware in the loop

Process control equipment

Medical devices

Équipement d'essai automatisé

Data acquisition system

Programmable voltage sources

Optical communications

 

THÉORIE DU FONCTIONNEMENT

Streaming Mode

When the SINGLE_INSTRUCTION bit in the INTERFACE_CONFIG_ B register is set to 0, single instruction mode is disabled and streaming mode is enabled. In streaming mode, multiple registers with adjacent addresses can be accessed with a single instruction phase and data phase, allowing efficient access of contiguous regions of memory (for example, during initial device configuration). The AD3541R is configured in streaming mode by default.

When in streaming mode, each SPI frame consists of a single instruction phase and the following data phase contains data for multiple registers with adjacent addresses. A starting register address is specified by the digital host in the instruction phase, and this address is automatically incremented or decremented (based on the address direction setting) after each byte of data is accessed. The data phase can, therefore, be multiple bytes long, and each consecutive byte of read or write data corresponds to the next higher or lower register address (for ascending and descending address direction, respectively).

When writing or reading from a multibyte register in streaming mode with address ascending, the user must address the least significant byte of the register in the instruction phase. The data phase starts transferring data from the least significant byte in first place.

When writing or reading from a multibyte register in streaming mode with the address descending, the user must start addressing the most significant byte of the register in the instruction phase. The data phase starts transferring the most significant byte in first place.

The STREAM_MODE register can be used to specify a range of consecutive registers to loop through in the data phase. Looping allows the digital host to repeatedly read from or write to a set of registers (for example, CHx_DAC_16B register at Address 0x29 to Address 0x2C) as efficiently as possible. When accessing register addresses after and including Address 0x29, the address direction must always be set as descending.